1. Field
Exemplary embodiments of the present invention relate to a phase mixer and a delay locked loop.
2. Description of the Related Art
A phase mixer is a circuit which mixes two signals with different phases and generates a mixed signal with an intermediate phase between the phases of the two signals. The phase of the mixed signal generated by the phase mixer is changed depending upon at which ratio the two signals are mixed. For example, if a first signal and a second signal are mixed at the ratio of M:N, as M/N increases, the phase of a mixed signal approaches the phase of the first signal, and as M/N decreases, the phase of a mixed signal approaches the phase of the second signal. Since the phase mixer can finely control the phase of a mixed signal between the phases of two signals, the phase mixer is used in a delay locked loop (DLL), etc.
FIG. 1 is a configuration diagram of a conventional phase mixer.
Referring to FIG. 1, the phase mixer includes a first driver 110, a second driver 120, and an buffer 130.
Hereinafter, operations of the phase mixer will be described with reference to FIG. 1.
The first driver 110 drives a first clock FCLK to a mixing node MN with a driving force that is determined in response to a code CD<0:3>. For this operation, the first driver 110 includes a plurality of inverters 111 to 114 which are activated or deactivated by the respective bits CD<0> to CD<3> of the code CD<0:3>.
The second driver 120 drives a second clock SCLK to the mixing node MN with a driving force that is determined in response to an inverted code CDB<0:3>, which is obtained by inverting the code CD<0:3>. According to an example, the second driver 120 includes a plurality of inverters 121 to 124, which are activated or deactivated by the respective bits CDB<0> to CDB<3> of the inverted code CDB<0:3>. For illustration purposes, the respective bits CD<0> to CD<3> of the code CD<0:3> and the respective bits CDB<0> to CDB<3> of the inverted code CDB<0:3> are in inverted relationships.
The buffer 130 buffers the signal of the mixing node MN and outputs the buffered signal to an output node OUT. For this operation, the buffer 130 may be an inverter which outputs a high level to the output node OUT when the voltage level of the mixing node MN is lower than a reference level (a logic threshold, that is, a reference voltage for discriminating a high level and a low level) and outputs a low level to the output node OUT when the voltage level of the mixing node MN is higher than the reference level.
The first driver 110 drives the first clock FCLK output to the mixing node MN more strongly as the number of bits with a high value of ‘1’ increases among the respective bits of the code CD<0:3>, and the second driver 120 drives the second clock SCLK output to the mixing node MN more strongly as the number of bits with a high value of ‘1’ increases among the respective bits of the inverted code CDB<0:3>. For example, if the value of the code CD<0:3> is ‘0001’ (the value of the inverted code CDB<0:3> is ‘1110’), a ratio between the driving force for driving the first clock FCLK to the mixing node MN and the driving force for driving the second clock SCLK to the mixing node MN becomes 1:3. If the value of the code CD<0:3> is ‘0111’ (the value of the inverted code CDB<0:3> is ‘1000’), a ratio between the driving force for driving the first clock FCLK to the mixing node MN and the driving force for driving the second clock SCLK to the mixing node MN becomes 3:1. If the value of the code CD<0:3> is ‘1111’ (the value of the inverted code CDB<0:3> is ‘0000’), for example, only the first clock FCLK is driven to the mixing node MN, and if the value of the code CD<0:3> is ‘0000’ (the value of the inverted code CDB<0:3> is ‘1111’), for example, only the second clock SCLK is driven to the mixing node MN. The phase of the signal (hereinafter, referred to as an output signal OUT) outputted to the output node OUT is changed according to the driving forces for driving the first clock FCLK and the second clock SCLK to the mixing node MN.
The phase mixer may be used as a fine delay line for finely controlling the phase of a clock in a delay locked loop (DLL). As to details of using a phase mixer as a fine delay line of a delay locked loop, such details are disclosed in Korean Patent Application No. 10-2009-0133426 (entitled “a delay locked loop circuit”), which is incorporated herein by reference in its entirety.
When a phase mixer is used in a delay locked loop, in order to suppress the occurrence of a jitter, a phase change amount in the output signal of the phase mixer is constant with respect to a change in the code CD<0:3>. That is to say, in the cases where the code CD<0:3> changes from ‘0000’ to ‘0001’, from ‘0001’ to ‘0011’, from ‘0011’ to ‘0111’ and from ‘0111’ to ‘1111’, the phase change amounts in the output signals of the phase mixer are the same with one another (namely, each time the value of the code CD<0:3> is changed by a unit value (for example, 1 bit), the phase of the output signal of the phase mixer is changed by a period equal to the unit value when the phase difference between the first clock FCLK and the second clock SCLK is divided into four equal periods).
In general, when the phase difference between the first clock FCLK and the second clock SCLK is small, the phase mixer operates as described above. However, as the phase difference between the first clock FCLK and the second clock SCLK increases, the phase mixer deviates from the above-described operations.
FIG. 2 is a waveform diagram illustrating a feature in the conventional phase mixer as the phase difference between the first clock FCLK and a second clock SCLK increases.
For illustration purposes, the waveforms of the first clock FCLK and the second clock SCLK are independently shown in FIG. 2 assuming that the code CD<0:3> is changed from ‘0000’ sequentially to ‘0001’, ‘0011’ and ‘0111’ (the inverted code CDB<0:3> is changed from ‘1111’ sequentially to ‘1110’, ‘1100’ and ‘1000’). The waveform of the signal (hereinafter, referred to as a “mixed signal MN”) generated at the mixing node MN corresponds to a waveform in which the waveform of the first clock FCLK and the waveform of the second clock SCLK are summed with each other (at each time, the sum of the value of the first clock FCLK and the value of the second clock SCLK becomes the value of the mixed signal MN).
Depending upon whether the level of the mixed signal MN is higher or lower than a reference level 201 (the mixed signal MN has a high level or a low level), a high level or a low level is outputted to the output node OUT. Therefore, times A1 to A4 at which the reference level 201 and the mixed signal MN cross each other correspond to times at which the logic value of the output signal OUT is changed. Thus, by observing how the times A1 to A4 at which the reference level 201 and the mixed signal MN cross with each other are moved as the value of the code CD<0:3> is changed, a change in the phase of the output signal OUT is changed as the value of the code CD<0:3> is determined.
Referring to FIG. 2, it can be seen that, when the phase difference between the first clock FCLK and the second clock SCLK is large, the phase change amounts 202, 203 and 204 of the output signal OUT are not constant as the code CD<0:3> is changed from ‘0000’ sequentially to ‘0001’, ‘0011’ and ‘0111’ (the phase change amounts 202, 203 and 204 gradually increase). In other words, when the phase difference between the first clock FCLK and the second clock SCLK is large, the phase change amounts of the output signal OUT are not constant even though the code CD<0:3> is sequentially changed by the unit value (for example, 1 bit). Due to such features, a jitter is likely to increase in the delay locked loop.